Integrated circuitry may be fabricated over and within semiconductor substrates. Individual device components of the circuitry may be separated or electrically isolated from other device components by dielectric or other isolation formed over and/or within the semiconductor substrate. One form of isolation is commonly referred to as trench isolation, wherein trenches are etched into semiconductor substrate material and subsequently filled with one or more dielectric materials. The trenches and isolation material therein may surround islands of semiconductor substrate material, commonly referred to as active area regions, where some of the individual circuit components are fabricated.
Integrated circuitry can be fabricated to have many functions, and may include many different electronic devices such as capacitors, transistors, resistors, diodes, etc. One type of electronic device is a recessed access device, which is a field effect transistor that has its gate construction received wholly or partially within a trench formed in semiconductor material. A gate dielectric separates the conductive gate from the semiconductor material. A pair of source/drain regions is formed within semiconductor material elevationally higher than the conductive gate materials. Application of suitable voltage to the conductive gate material within the trench enables current to flow through the semiconductor material between the source/drain regions along the trench sidewalls and around the base of the trench. The gates of recessed access devices in some circuit constructions transversally cross some active area regions and extend between other immediately end-to-end adjacent active area regions. Due to proximity of the gate material of a recessed access gate line passing between and close to the ends of active area regions, adverse circuit operation may occur. Such problems include parasitic coupling and adverse sub-threshold current leakage. Problems such as these may be mitigated by increasing the end-to-end spacing between active area regions and/or reducing the width of the recessed access gate lines. However, such techniques may have their own adverse effects.
Another challenge in integrated circuitry fabrication is interconnection of conductive lines to lower elevation circuit components. As circuit components become smaller and closer together, it becomes increasingly difficult to control critical dimension, mask alignment, and provide acceptable margins of error when forming contact openings to the lower elevation circuit components.